Intel 8. 08. 6 - Wikipedia, the free encyclopedia. Intel 8. 08. 6Produced. From 1. 97. 8 to 1. Common manufacturer(s)Intel, AMD, NEC, Fujitsu, Harris (Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi, Panasonic (Matsushita). Max. CPUclock rate. MHz to 1. 0 MHz. Min. The Intel 8. 08. 8, released in 1. ICs. The device needed several additional ICs to produce a functional computer, in part due to it being packaged in a small 1. It had an extended instruction set that was source (not binary) compatible with the 8. The 8. 08. 0 device, often described as . It was an attempt to draw attention from the less- delayed 1. Motorola, Zilog, and National Semiconductor) and at the same time to counter the threat from the Zilog Z8. Intel employees), which became very successful. Both the architecture and the physical chip were therefore developed rather quickly by a small group of people, and using the same basic microarchitecture elements and physical implementation techniques as employed for the slightly older 8. Marketed as source compatible, the 8. The programming model and instruction set was (loosely) based on the 8. However, the 8. 08. New kinds of instructions were added as well; full support for signed integers, base+offset addressing, and self- repeating operations were akin to the Z8. Overview of architecture 8087. Interfacing with 8086. Data types, instructions. STATUS;copy status word to AX to check; bits ( a)Instructions directly supporting nested. ALGOL- family languages such as Pascal and PL/M were also added. According to principal architect Stephen P. Morse, this was a result of a more software centric approach than in the design of earlier Intel processors (the designers had experience working with compiler implementations). Other enhancements included microcoded multiply and divide instructions and a bus structure better adapted to future coprocessors (such as 8. The first revision of the instruction set and high level architecture was ready after about three months. It was soon moved to a new refined n. MOS manufacturing process called HMOS (for High performance MOS) that Intel originally developed for manufacturing of fast static RAM products. Morse with some help and assistance by Bruce Ravenel (the architect of the 8. Logic designer Jim Mc. Kevitt and John Bayliss were the lead engineers of the hardware- level development team. The legacy of the 8. Intel 2. 86 and the Intel 3. OPERAND1 OPERAND2 1 Reg Reg 2 Reg Mem. Interrupts of 8086/8088 Microprocessor. Accumulator, B register and register banks (R0-R7), Program status word (PSW), Stack pointer (SP). What is the maximum memory 8088 can access? Write a program in assembly language that calculates the square of six by adding six to the. When read as a word it is 0005 but when written in memory it will. A 2. 0- bit external address bus provides a 1 MB physical address space (2. This address space is addressed by means of internal memory . The data bus is multiplexed with the address bus in order to fit all of the control lines into a standard 4. It provides a 1. 6- bit I/O address bus, supporting 6. KB of separate I/O space. The maximum linear address space is limited to 6. KB, simply because internal address/index registers are only 1. Programming over 6. KB memory boundaries involves adjusting the segment registers (see below); this difficulty existed until the 8. Some of the control pins, which carry essential signals for all external operations, have more than one function depending upon whether the device is operated in min or max mode. The former mode was intended for small single- processor systems, while the latter was for medium or large systems using more than one processor. Registers and instructions. Four of them, AX, BX, CX, DX, can also be accessed as twice as many 8- bit registers (see figure) while the other four, BP, SI, DI, SP, are 1. Due to a compact encoding inspired by 8- bit processors, most instructions are one- address or two- address operations, which means that the result is stored in one of the operands. At most one of the operands can be in memory, but this memory operand can also be the destination, while the other operand, the source, can be either register or immediate. A single memory location can also often be used as both source and destination which, among other factors, further contributed to a code density comparable to (and often better than) most eight- bit machines at the time. The degree of generality of most registers are much greater than in the 8. However, 8. 08. 6 registers were more specialized than in most contemporary minicomputers and are also used implicitly by some instructions. While perfectly sensible for the assembly programmer, this made register allocation for compilers more complicated compared to more orthogonal 1. PDP- 1. 1, VAX, 6. On the other hand, being more regular than the rather minimalistic but ubiquitous 8- bit microprocessors such as the 6. MCS- 4. 8, 8. 05. Another factor for this was that the 8. Pascal and PL/M; some of the more useful instructions were pushmem- op, and retsize, supporting the .
There are 2. 56 interrupts, which can be invoked by both hardware and software. The interrupts can cascade, using the stack to store the return addresses. The 8. 08. 6 has 6. K of 8- bit (or alternatively 3. K of 1. 6- bit word) I/O port space. Nine of these condition code flags are active, and indicate the current state of the processor: Carry flag (CF), Parity flag (PF), Auxiliary carry flag (AF), Zero flag (ZF), Sign flag (SF), Trap flag (TF), Interrupt flag (IF), Direction flag (DF), and Overflow flag (OF). Segmentation. Rather than concatenating the segment register with the address register, as in most processors whose address space exceeded their register size, the 8. As a result, each external address can be referred to by 2. Segment,1. 6 bits, shifted 4 bits left+ 0. Offset,1. 6 bits 0. Address,2. 0 bits. Although considered complicated and cumbersome by many programmers, this scheme also has advantages; a small program (less than 6. KB) can be loaded starting at a fixed offset (such as 0. Compilers for the 8. Near pointers are 1. Far pointers are 3. Some compilers also support huge pointers, which are like far pointers except that pointer arithmetic on a huge pointer treats it as a linear 2. To avoid the need to specify near and far on numerous pointers, data structures, and functions, compilers also support . The tiny (max 6. 4K), small (max 1. K), compact (data > 6. K), medium (code > 6. K), large (code,data > 6. K), and huge (individual arrays > 6. K) models cover practical combinations of near, far, and huge pointers for code and data. The tiny model means that code and data are shared in a single segment, just as in most 8- bit based processors, and can be used to build . Precompiled libraries often came in several versions compiled for different memory models. According to Morse et al.. However, as this would have forced segments to begin on 2. MB was considered very large for a microprocessor around 1. Also, there were not enough pins available on a low cost 4. In principle, the address space of the x. This would mean that all instruction object codes and data would have to be accessed in 1. Users of the 8. 08. By having a large number of 8- bit object codes, the 8. The first 8- bit opcode will shift the next 8- bit instruction to an odd byte or a 1. By implementing the BHE signal and the extra logic needed, the 8. If memory addressing is simplified so that memory is only accessed in 1. Intel decided to make the logic more complicated, but memory use more efficient. This was at a time when memory size was considerably smaller, and at a premium, than that which users are used to today. This allowed 8- bit software to be quite easily ported to the 8. The authors of MS- DOS took advantage of this by providing an Application Programming Interface very similar to CP/M as well as including the simple . CP/M. This was important when the 8. MS- DOS were new, because it allowed many existing CP/M (and other) applications to be quickly made available, greatly easing acceptance of the new platform. Example code. The data block is copied one byte at a time, and the data movement and looping logic utilizes 1. This kind of calling convention supports reentrant and recursive code, and has been used by most ALGOL- like languages since the late 1. The above routine is a rather cumbersome way to copy blocks of data. The 8. 08. 6 provides dedicated instructions for copying strings of bytes. These instructions assume that the source data is stored at DS: SI, the destination data ist stored at ES: DI, and that the number of elements to copy is stored in CX. The above routine requires the source and the destination block to be in the same segment, therefore DS is copied to ES. The loop section of the above can be replaced by. FC. 0. 00. 0: 1. 01. F2. 0. 00. 0: 1. 01. A4. cld; Copy towards higher addresseslooprepnz; Repeat until CX=0movsb; Move the data block. This copies the block of data one byte at a time. The REPNZ instruction causes the following MOVSB to repeat until CX is zero, automatically incrementing SI and DI and decrementing CX as it repeats. Alternatively the MOVSW or MOVSD instructions can be used to copy 1. CX counts the number of words copied instead of the number of bytes). Most assemblers will properly recognize the REPNZ instruction if used as an in- line prefix to the MOVSB instruction, as in REPNZ MOVSB. This routine will operate correctly if interrupted, because the program counter will continue to point to the REP instruction until the block copy is completed. The copy will therefore continue from where it left off when the interrupt service routine returns control. Performance. As instructions varied from one to six bytes, fetch and execution were made concurrent and decoupled into separate units (as it remains in today's x. The bus interface unit fed the instruction stream to the execution unit through a 6- byte prefetch queue (a form of loosely coupled pipelining), speeding up operations on registers and immediates, while memory operations unfortunately became slower (four years later, this performance problem was fixed with the 8. However, the full (instead of partial) 1. ALU meant that 1. ALU cycle (instead of two, via internal carry, as in the 8. Combined with orthogonalizations of operations versus operand types and addressing modes, as well as other enhancements, this made the performance gain over the 8.
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